Statistical variation plays an important role in circuit design efforts, particularly in advanced semiconductor fabrication processes, such as those with feature sizes below forty-five nanometers. Device mismatch variation is of particular concern. Circuit designers should therefore consider statistical variation when running circuit simulations.
Designers rely on Monte Carlo analysis to approve designs with the reduced feature sizes that are common nowadays. Monte Carlo analysis involves simulating a circuit with a wide range of randomly chosen device samples. The result is a distribution of predicted circuit behaviors that may be used to guide circuit design evolution. Thousands of such simulations are often needed.
It is currently computationally expensive to run a Monte Carlo analysis because each Monte Carlo iteration is a completed circuit simulation run, including device model parsing and calculation, and then real circuit analysis. It may generally be infeasible to run Monte Carlo simulations via conventional SPICE circuit analyses on large circuits, because each iteration may take hours.
Recent developments in so-called Fast SPICE technologies may achieve up to 100× speed increases compared to conventional SPICE circuit simulation. The state of the art Fast SPICE technology, however, has an inherent two to five percent inaccuracy compared to full SPICE circuit simulation. Circuit designers will want to know how the up to five percent Fast SPICE error impacts the final output result distributions in statistical simulations. More broadly, designers want to determine how Fast SPICE technology may be best leveraged for fast and relatively accurate statistical analysis capability.
Accordingly, the inventors have developed a novel method to quickly and accurately capture device model statistical variation for use with conventional SPICE simulators and the improved Fast SPICE simulation tools.